5.2	The WFC3 UVIS Channel CCD Detectors

5.2.1 Basics of CCD Operation

5.2.2 The WFC3 CCDs

5.2.1 Basics of CCD Operation

A charge-coupled device (CCD) is a silicon-based detector containing a two-dimensional array of summing wells called pixels, short for pixel elements. Each pixel accumulates electric charge in proportion to the number of photons striking that location on the detector. Physically, the summing wells are created by electric fields established at the depletion (charge-free) regions of the Si-SiO2 metal-oxide-semiconductor (MOS) capacitors. In a typical three-phase CCD, the size of the depletion region is controlled by the voltage of three gates. The gates are arranged in parallel, with every third gate connected together.

At the end of an exposure, the voltages of the gates are changed with an appropriate clocking pattern, causing all charge packets to be sequentially transferred to the adjacent pixel, until they reach the readout circuitry at the detector’s edge. The transfer of charges between pixels occurs in parallel, row by row, whereas the extraction of the “zeroth” row at the edge occurs along an external serial register, where each packet is serially transferred to an output amplifier at the detector corner.

5.2.2 The WFC3 CCDs

The WFC3 UVIS channel uses two CCD detectors fabricated by e2v Ltd. (formerly Marconi Applied Technologies Ltd.). Both CCDs are 2051×4096 devices with 15×15 μm square pixels. There are 2051 rows by 4096 columns, where the row/columns definition follows the convention of having the parallel direction first and the serial direction second. Having the serial register along the long (4096 pixel) edge reduces the number of transfers required to read out a charge packet.

The WFC3 CCDs are three-phase devices, thinned and back-illuminated (back-thinned) to improve the sensitivity to UV light. Thinning refers to the removal of the thick substrate on which the chip is originally built and is done to improve shorter-wavelength efficiency (only those electrons generated in the vicinity of the gate structure can be collected efficiently). Back-illumination means that photons are focussed on the back side of the chip, rather than having to pass through the opaque gate structures implanted on the front side.

Similar to ACS, the WFC3 CCDs also have buried channels and are operated in multi-pinned phase (MPP) mode. This buried channel, or mini-channel, improves CTE for targets with relatively low signal levels (~10K e– or less) and reduces the dark current as well. The buried channels have the capability of injecting charges to fill in the traps and improve the CTE (but observers should see Section 6.9.2). Further details of these features are given in Section 5.4.8.

The two WFC3 CCDs are butted together along their long dimension to create a 2×1 mosaic. Figure 5.1 shows a picture of a CCD assembly similar to the flight detector. The butted configuration is equivalent to a 4102×4096 array, but with a gap of 31 ± 0.1 pixels between the two chips (1.2 arcsec on the sky).

The CCDs are cooled by a four-stage thermoelectric cooler (TEC) to a nominal temperature of −83° C. The detectors are packaged inside a cold enclosure, which is nearly identical to the one used for ACS, itself a scaled-up version of the STIS design. The package includes a second cooled window to reduce the radiative heat load.

The CCD focal plane is assembled on a molybdenum (moly) base disk, which provides some shielding from cosmic rays and also serves as the thermal sink path from the hot side of the TEC stack to the heat pipes (which carry the heat to the external radiator). The “cover” with the external window is about 1 cm thick and is made of “alloy 42" steel; it provides some protection from CRs incident on the front side of the CCDs.

The WFC3 CCDs are quite similar to those used in the ACS Wide Field Channel (WFC). They have the same pixel size, nearly the same format (2051×4096 in WFC3, compared to 2048×4096 in ACS), the same orientation of the serial and parallel registers, similar technology (buried-channel, MPP operation), and nearly identical mechanical interfaces. The main differences of the WFC3 chips compared to those in ACS/WFC are:

•	UV optimization of the WFC3 wavelength response

•	Significantly lower readout noise for the WFC3 chips (~3.1- 3.2 e- compared to 3.9-4.6 e- )

•	2051 rows instead of 2048

•	Charge-injection capability for mitigation of degradation in CTE due to on-orbit radiation damage (not generally available for science observations; see Section 6.9.2)

•	31-pixel gap instead of 50

•	Manufactured by e2V (formerly Marconi); ACS has Site devices.

An overview of the WFC3 CCD performance was given above in Table 5.1.

Figure 5.1: Detector package similar to the WFC3/UVIS flight detector. The size of the 4kx4k array is approximately 6×6 cm, and it consists of two butted 2051×4096 CCDs with a 31-pixel gap between them.