CMOS ACTIVE PIXEL SENSORS: capabilities, status, and future

-          B. Pain

Ever since the invention of charge coupled devices (CCD) in 1970, CCD technology has emerged as the standard-bearer for large format visible imager implementation. The predominance of CCD was due to its superior sensitivity, dynamic range, uniformity, low noise, and small pixel size. However CCDs require specialized silicon processing that is not compatible with CMOS technology. Furthermore, CCDs are high capacitance devices, requiring multiple non-standard and high voltage clocks and biases, while providing only serial output through repetitive charge transfer, precluding random access to pixels. High device capacitance, large clock swing, need for DC-DC converters, and inability to integrate control & processing electronics on the imager chip make the CCD-based imaging system bulky and power-hungry (camcorder CCD power dissipation is around 10 W).

While CMOS visible imaging technology predates CCDs [1], these devices operated with large temporal and spatial noise, and were not suitable for large format implementation. These limitations resulted from the use of passive pixels. In 1970s and 80s, CMOS imagers were forced to use passive pixels in order to provide high fill-factor even with relatively large minimum feature sizes (>2 mm). The situation changed in 1990s with the widespread advent of sub-micron fabrication technology, and an unchallenged predominance of CMOS VLSI in consumer electronics from cell-phones and televisions to personal computers. Sub-micron feature sizes enabled the use of active pixel concepts, setting the stage for reemergence of CMOS technology for high-performance visible imager implementation.

An active pixel (APS) refers to the incorporation of MOSFETs in the pixel in a manner that charge to a buffered signal (voltage or current) occurs at the pixel itself. This way, the need for charge transfer over a long bus (either through repetitive transfer or via charge-sharing) is eliminated, enabling implementation of high performance imager in CMOS technology. Since the pixel is implemented in CMOS techonology, unlike a CCD, an APS is capable of integrating not only the pixel array, but also of all the timing and control, digitization, interface control, and bias circuits in one chip, resulting in a compact low-power “camera-on-a-chip”.

CMOS APS can potentially  provide significant advantages for scientific applications. These advantages include: (i) low-power (~ 10 mW), (ii) ease of operation with a simple interface and without the need for critical biasing, (iii) random access for zooming onto phenomena of interest, (iv) constancy of read noise with operating speed and higher speed of operation – both of which assume critical importance for ultra-large format imager implementation, (v) excellent anti-blooming (10000x saturation), (vi) larger signal handling capacity, (vii) operation over a large range of temperatures (77K to 300K), (viii) availability of smart features e.g. different exposure times for different parts of the field of view within the same frame, and a (ix) high level of radiation tolerance (> 10 Mrad). In addition, CMOS imagers can also be used as readout elements with other technologies – such as MCP detectors and AlGaN.

Contrary to the commonly-held perception that device scaling is deleterious for CMOS imager performance, deep sub-micron technology is actually beneficial to improving CMOS imager performance. All deep sub-micron technology uses a twin-well process with shallow trench isolation. Apart from providing higher fill-factor, the use of a twin-well allows better CMOS imager operation with high QE and MTF, once the epitaxial silicon thickness is appropriately chosen, and its doping is decreased. Decrease in doping is also required by VLSI circuits, independent of imager operation, in order to eliminate substrate cross-talk. Hence, requirements of VLSI circuit performance enhancement is similar to that needed for imager performance enhancement. Secondly, a number of source-drain engineering techniques used for implementing MOSFETs in deep sub-micron technology will also improve pixel linearity. Thirdly, methods used for preventing hot-electron effects in CMOS devices will also make it more radiation-hard, since the two effects are nearly identical. Hence, CMOS imagers will retain high radiation tolerance with technology scaling. Finally, several foundries are working on integrating 0.18 mm and 0.5 mm technologies that includes multi-threshold FETs, and high voltage (>3.3V) operation, providing large signal handling capacity even with deep sub-micron technologies. One of the key problems to be resolved is the reduction of dark current.

Summarized below are the key issues that need resolution in order to allow entry of CMOS imagers into the scientific applications area, and outlook for resolution.

  1. Increase of format: While high quality 1Kx1K devices are becoming available, 10Megapixel devices are expected to be available within the next two years. Larger format devices will require reticle stitching (a service provided by most advanced CMOS foundries). For billion pixel imagers, new buttable architectures with efficient methods for extraction of focal-plane data is needed. CMOS technology appears best suited for such purposes by using a 3-D stack consisting of a reverse-illuminated imager, a readout chip and through silicon vias for connection. Both Nanosciences Corp and Tru-Si Inc. possess the techonology for through silicon via implementation.
  2. Reduction of dark current: High quality CCD dark currents are in 1-20 pA/cm2 range. On the other hand, CMOS imager dark currents are ~ 100-2500 pA/cm2, with higher dark current non-uniformities than is encountered with CCDs. Solution to the problem includes passivation implants at STI edges, low-energy implants for device layer (i.e. the well), and additional surface implants. In this connection, an imager implemented in SOI technology may provide a significant advantage, since the photodiode is placed in a planar region, enabling easier application of passivation implants. Lastly, newer pixel designs with lower perimeter values will also help the situation significantly.
  3. Reduction of read noise: APS noise is ~ 20-30 electrons at room temperature. New circuit techniques are becoming available for beating the “fundamental” kTC noise limit to enable near CMOS imagers with 1 e—or sub-electron read noise.
  4. Reduction of fixed pattern noise:  a mixture of on-chip circuit techniques and off-chip calibration should reduce fixed pattern noise below read noise limits.
  5. Improving linearity:  Improving linearity has two components – low light level and overall. Use of analog column circuits allowing the imager pixel to be reset in flushed reset (preset followed by soft-reset) provides excellent low-light linearity (better than 0.1% INL), low noise (2x lower), zero image lag, and largest dynamic range. Improvement of linearity over the entire signal range can be obtained by appropriate signal chain circuit design, and through advanced processing techniques (source-drain engineering) to improve diode linearity.
  6. Improving QE and MTF: QE and MTF can be increased by appropriate choice of epitaxial silicon doping and thickness. Highest QE and MTF is achieved either by using thinned and backside-illuminated CMOS pixels or by using a hybrid p-I-n detector approach. While both approaches are technically viable, it is unclear which one will prove to be the most reliable one.

In conclusion, the main propellants that fuel the growth of CMOS imagers is the ubiquitous presence of CMOS VLSI and an emerging consumer market far beyond conventional camcorder applications. Although CMOS imagers developed for consumer applications are not directly applicable to scientific applications, NASA is in a good position to exploit the huge CMOS fabrication infrastructure to develop CMOS imagers suited for its use. In other words, NASA must establish collaborative working relationships not only with imager chip manufacturers, but also with the foundry themselves. Attention must also be paid to the fact that during economic downturns, many foundries are more open to changing their microfabrication processes than at other times. With a global slowdown possibly round the corner, this may open up a window of opportunity to fine tune fabrication processes to suit NASA’s needs, while brining benefit to the commercial sector. Another important concern is the absence of commercially available CMOS foundries in US.

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